ALTERA TERASIC USB BLASTER DRIVER

While the Terasic was rock solid in its communication with the Color3 board. We see a similar pattern, but interestingly enough, it’s not the same. But the cheap clone runs TCK at exactly double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable. If we ignore for a second that the cheap clone doesn’t work on this particular board, the biggest consequence of the chapeau clone is that bulk transfers are much slower: We have a prefix with 8 slow clocks, but in between the second and the third slow clock, there’s a signal fast clock group.

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We see a similar pattern, but interestingly enough, it’s not the same. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today: The Terasic doesn’t have that problem: For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan DR or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of a scan data register.

There are 3 major sections: My money is on the clock speed: When you zoom in ueb the slow clock cycles, you can measure a TCK frequency of kHz: We have a prefix with 8 slow clocks, but in between the second altega the third slow clock, there’s a signal fast clock group. It looks like the cheap clone is able to squeeze out bits really fast, but there’s quite a bit of software overhead in processing the next byte in the USB packet.

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:: Terasic Inc. – Expertise in FPGA/ASIC Design ::

It’s not that it’s broken: In addition, there are roughly 3 idle cycles between a fast clock group. While the Terasic was rock solid in its communication with the Color3 board.

If we ignore for a second that the cheap alltera doesn’t work on this particular board, the blater consequence of the chapeau clone is that bulk transfers are much slower: The most important signal here is TCK, in yellow. In the middle we have the expected 16 fast clock groups.

This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command. About Us Contact Hackaday. The set of signals below that is a slightly zoomed in version of the one above. Yes, delete it Cancel. As I wrote earlierthe biggest issue with the cheap clone is that it doesn’t work on my eeColor Color3 board.

A really interesting difference is in the spacing between fast clock groups: And here’s the equivalent of the cheap clone.

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Terasic vs Cheap Clone USB Blaster

For the overview, look at the upper set. For the cheap clone, the spacing is huge: It may be that 12MHz terasif really just pushing things too much.

In the middle there are 16 groups with fast clock cycles each group is itself 8 clock cycles. A fast clock group sets the clock at 12MHz instead of 6MHz. altea

Sign up Already a member? Zooming in on the slow clocks, we see a clock frequency of kHz.

The suffix is really different, with 6 clock clocks but also a fast clock group in between. Meanwhile, during rerasic fast clock group, the clock toggles at 6MHz. What remains is the question about why the cheap clone doesn’t work.

But the cheap clone runs TCK at bkaster double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable. And at the end you have a suffix with 2 slow clock cycles. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today:.